Conventionally, clock gating has been performed on an unused latch circuit to reduce the power consumption of an electric circuit. The clock gating refers to stopping the supply of a clock to a portion where and when it is known in advance that an input is not changed. However, in a latch circuit to be used, the supply of a clock cannot be stopped, thereby failing in reducing the power consumption.
Then, input/output data signals of the latch circuit are compared with each other, and when they match, the propagation of an input clock into the inner portion of the latch circuit is suppressed. FIG. 1 illustrates an example of a latch circuit having the function of suppressing the clock propagation into the internal portion.
A latch circuit 10 illustrated in FIG. 1 includes a data input terminal 11, a data output terminal 12, a clock input terminal 13 for input of a inverted clock, and an IH (inhibit) pin 14 for input of a control signal for suppressing the clock propagation in a latch. The latch circuit provided with an IH pin in FIG. 1 is referred to as the IH latch circuit 10.
FIG. 2 is a block diagram of the circuit in FIG. 1. The clock input terminal 13 and the IH pin 14 are connected to a clock internal propagation suppressing unit 21, and an internal clock signal XCLK for which the propagation control of a clock has been performed by the clock internal propagation suppressing unit 21 is input to a latch unit 22. The latch unit 22 holds an input value outputs it. The internal clock signal XCLK and the data signal from the data input terminal 11 are input to the latch unit 22, and the latch unit 22 outputs the data signal to the data output terminal 12.
FIG. 3 is an example of a detailed configuration of the IH latch circuit 10 illustrated in FIGS. 1 and 2. The circuit includes P-channel MOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistors) P1, P2, P3, P4, P5, P6, P7, and P8, and N-channel MOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistors) N1, N2, n3, N4, N5, N6, N7, and N8. In the descriptions below, the P-channel MOSFET is described as a PMOS transistor, and the N-channel MOSFET is described as an NMOS transistor.
The source terminal of the PMOS transistor P1 is connected to a high-voltage side power supply terminal (VDD), and the gate terminal is connected to the IH pin 14. The source terminal of the PMOS transistor P2 is connected to the drain terminal of the PMOS transistor P1, and the gate terminal is connected to the clock input terminal 13. The source terminal of the NMOS transistor N1 is connected to the low-voltage side power supply terminal (VSS), the gate terminal is connected to the clock input terminal 13, and the drain terminal is connected to the drain terminal of the PMOS transistor P2. The source terminal of the NMOS transistor N2 is connected to the low-voltage side power supply terminal, the gate terminal is connected to the IH pin 14, and the drain terminal is connected to the drain terminals of the PMOS transistor P2 and the NMOS transistor N1.
The portion (enclosed by the dotted lines in FIG. 3) configured by the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 corresponds to the clock internal propagation suppressing unit 21 in FIG. 2. That is, this portion controls the internal propagation of a clock signal. When the control signal for suppression of the internal propagation of the clock signal (hereafter referred to as an IH signal) indicates a high level (hereafter described by H), the PMOS transistor P1 is placed in the OFF state, the NMOS transistor N2 is placed in the ON state, and the internal clock signal XCLK is constantly placed at the low level (hereafter described by L). That is, when the IH signal indicates H, the propagation of the clock signal from the clock input terminal 13 is suppressed. On the other hand, when the IH signal indicates L, and the inverted clock input from the clock input terminal 13 indicates L, the PMOS transistors P1 and P2 are placed in the ON state, the NMOS transistors N1 and N2 are placed in the OFF state, and the internal clock signal XCLK indicates H. Furthermore, if the IH signal indicates H and the inverted clock input from the clock input terminal 13 indicates H, then the PMOS transistors P1 and P2 are placed in the OFF state, the NMOS transistors N1 and N2 are placed in the ON state, and the internal clock signal XCLK indicates L. Thus, when the IH signal indicates L, the inverted result (signal) of the inverted clock input from the clock input terminal 13 is propagated as the internal clock signal XCLK to the latch unit 22.
The portion corresponding to the latch unit 22 in FIG. 2 is described below.
The source terminal of the PMOS transistor P3 is connected to the high-voltage side power supply terminal, and the internal clock signal XCLK is input to the gate terminal. The source terminal of the NMOS transistor N3 is connected to the low-voltage side power supply terminal, the internal clock signal XCLK is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P3. The PMOS transistor P3 and the NMOS transistor N3 configure an inverter (negation circuit).
The source terminal of the PMOS transistor P4 is connected to the high-voltage side power supply terminal, and the gate terminal is connected to the data input terminal 11. The source terminal of the NMOS transistor N4 is connected to the low-voltage side power supply terminal, the gate terminal is connected to the data input terminal 11, and the drain terminal is connected to the drain terminal of the PMOS transistor P4. The PMOS transistor P4 and the NMOS transistor N4 configure an inverter.
The source terminal of the PMOS transistor P5 is connected to the drain terminals of the PMOS transistor P4 and the NMOS transistor N4, and the gate terminal is connected to the drain terminals of the PMOS transistor P3 and the NMOS transistor N3. The source terminal of the NMOS transistor N5 is connected to the drain terminals of the PMOS transistor P4 and the NMOS transistor N4, and the internal clock signal XCLK is input to the gate terminal. The PMOS transistor P5 and the NMOS transistor N5 as pass transistors configure a transfer gate 20. When the gate terminal of the PMOS transistor P5 indicates N, and the gate terminal of the NMOS transistor N5 indicates H, a signal obtained by inverting the input data signal input from the data output terminal 12 is output as the data signal PCM1.
The source terminal of the PMOS transistor P6 is connected to the high-voltage side power supply terminal, and the data signal PCM1 is input to the gate terminal. The source terminal of the NMOS transistor N6 is connected to the low-voltage side power supply terminal, the data signal PCM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P6. The PMOS transistor P6 and the NMOS transistor N6 configure an inverter, invert the data signal PCM1, and outputs the data signal PAM1.
The source terminal of the PMOS transistor P7 is connected to the high-voltage side power supply terminal, and the data signal PAM1 is input to the gate terminal. The source terminal of the NMOS transistor N7 is connected to the low-voltage side power supply terminal, the data signal PAM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P7. The PMOS transistor P7 and the NMOS transistor N7 configure an inverter, invert the data signal PAM1, and output the data signal PCM1.
The loop portion by two inverter circuits configured by the PMOS transistors P6 and P7 and the NMOS transistors N6 and N7 has the function of holding the latch data.
The source terminal of the PMOS transistor P8 is connected to the high-voltage side power supply terminal, and the data signal PCM1 is input to the gate terminal. The source terminal of the NMOS transistor N8 is connected to the low-voltage side power supply terminal, the data signal PCM1 is input to the gate terminal, and the drain terminal is connected to the drain terminal of the PMOS transistor P8. The PMOS transistor P8 and the NMOS transistor N8 configure an inverter, invert the data signal PCM1, and output it to the data output terminal 12.
The portion configured by the PMOS transistors P3, P4, P5, P6, P7, and P8 and the NMOS transistors N3, N4, N5, N6, and N7 corresponds to the latch unit 22 in FIG. 2.
In the IH latch circuit 10 as illustrated in FIGS. 1 through 3, it is necessary to compare input/output data signals, and input the result to the IH pin 14 as a control signal. In the comparing operation, an ENOR circuit (Exclusive-NOR circuit) and an exclusive-OR circuit (Exclusive-OR circuit)) are used. FIG. 4 is an example of using the ENOR circuit 41 in comparing the input/output data signals.
As illustrated in FIG. 4, the data signal input from the data input terminal 11 of the IH latch circuit 10 illustrated in FIG. 1 and the data signal output to the data output terminal 12 are input to an ENOR circuit 41 for comparison. The result of the data comparison is output to the IH pin 14. The ENOR circuit 41 outputs H if the two input signals match each other, and outputs L if they do not match each other. That is, if the input/output data signals match each other, the H is input to the IH pin 14, and if the input/output data signals do not match each other, the L is input to the IH pin 14. Thus, if the input/output data signals match each other, the internal propagation of the clock of the IH latch circuit 10 is suppressed, and if the input/output data signals do not match each other, the clock is propagated in the IH latch circuit 10.
FIG. 5 is a timing chart of the case in which the IH pin 14 is clipped (pulled down) to L (connected to the low-voltage side power supply terminal), that is, a timing chart indicating the state in which there is no IH pin. FIG. 6 is a timing chart of the case in which the result of inputting the input/output data signals of the IH latch circuit 10 to the ENOR circuit 41 is input to the IH pin 14 as with the circuit illustrated in FIG. 4.
When the IH pin 14 is clipped to L, the clock propagation in the IH latch circuit 10 is not controlled. Therefore, the internal clock signal XCLK is a inverted signal of the signal input to the clock input terminal 13 as illustrated in the timing chart in FIG. 5. On the other hand, when the IH pin 14 is connected to the output of the ENOR circuit 41, the clock propagation in the IH latch circuit 10 is controlled depending on whether or not the input/output data signals of the IH latch circuit 10 match each other. As illustrated in the timing chart in FIG. 6, when the input data signal D and the output data signal M indicate L (in the case of timing 1), and when the input data signal D and the output data signal M indicate H (in the case of timing 3), the IH1 as an output signal from the ENOR circuit 41 indicates H. Thus, the internal clock signal XCLK in the IH latch circuit 10 indicates L. As described above, since the internal propagation of the clock signal can be suppressed when the input/output data signals match in the circuit illustrated in FIG. 4, the power consumption of the IH latch circuit 10 can be reduced.
However, the ENOR circuit 41 for comparison of the input/output data signals requires at least 10 transistors as illustrated in FIG. 7. This implies the problem of a large number of transistors configuring the circuit. In addition, as illustrated in FIG. 7, the input data signal input from the input terminal A2 requires driving two transistors, that is, a PMOS transistor P71 and an NMOS transistor N71. However, the input data signal input from the input terminal A1 requires driving four transistors, that is, PMOS transistors P74 and P75, and NMOS transistors N73 and N74. Thus, the input capacitance (fan in capacitance) driven by an input data signal is approximately double that of the normal circuit, and the corresponding power consumption increases.